1. Field of the Invention
The present invention generally relates to Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs) and, more particularly, to an Interlocked Pipelined CMOS (IPCMOS) family of logic circuits.
2. Background Description
Circuit techniques are key to implementing the interlocked pipelined approach. In order for the approach to be viable, the circuit techniques must be extremely fast, simple, reliable , and very efficient. The general concepts of handshaking or interlocking and pipelining and asynchronous self-timing are not new and have all been proposed in a variety of forms for systems.
The Muller C-element described by Carver Mead and Lynn Conway in Chapter 7 of Introduction to VLSI Systems, published by Addison-Wesley Publishing Company Inc. (1980), and shown in FIG. 18 is a bistable device whose output becomes a "1" only after all of its inputs are "1" and whose output becomes a "0" only after all of its inputs are "0". The major problem with this circuit, aside from speed issues for large fan-ins, is that all its inputs must overlap for both the "0" and "1" cases or there will be no change in the output state. For complex interconnections of circuit blocks, commonly called macros, that have different speeds and interconnections this may not be the case and the circuit will not perform the intended function.
Another self-timed element and a two-cycle signaling scheme described by Ivan E. Sutherland in "Micropipelines", Communications of the ACM, vol. 32, Number 6, pp. 720-738, June 1989, and in the book by Mead and Conway is given in FIG. 19. In this scheme, the elements pass data to each other using Request and Acknowledge lines to control the sequence in an asynchronous fashion as shown in the wave forms. Aside from not dealing with how to solve the problem of multiple macros being interconnected, this approach is slow since the Acknowledge signal as shown in the wave forms is initiated when the output of the macro reaches a stable state. This means that after data is received, the macro must do its function before sending an acknowledgment which inserts additional delay in the cycle time.
Control logic with completion information embedded within data signals is used in a self-timed divider described by T. E. Williams et al. in "A Zero-Overhead Self-Timed 160 ns 54-b CMOS Divider", IEEE J. Solid State Circuits, vol. 26, pp. 1651-1661, November 1991. In this design, local completion detectors and handshaking between fully asynchronous macros is used. The completion information is embedded in the data throughout the design by using a pair of wires for each bit. The individual completion signals from the bits in a data path are then combined using a C-element similar to the one described above. This approach needs dual wires for each data signal plus it faces the limitations of the C-element already mentioned above.
Fully pipelined architectures have been used to obtain very fast cycle times in SRAMs, as described by T. I. Chappel et al. in "A 2-ns Cycle, 3.8-ns Access 512-Kb CMOS ECL SRAM with a Fully Pipelined Architecture", IEEE J Solid-State Circuits, vol. 26, pp. 1577-1585, November 1991. This approach works well in a very regular environment such as one finds in memory, but is extremely difficult or impossible to implement in a more general environment without some kind of handshaking to guarantee reliable operation.